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rev. 1.3 5/15 copyright ? 2015 by silicon laboratories si826x si826x 5 k v led e mulator i nput , 4.0 a i solated g ate d rivers features applications safety regulatory approvals description the si826x isolators are pin-compatible , drop-in upgrades for popular opto- coupled gate drivers, such as 0.6 a acpl-0302/3020, 2.5 a hcpl-3120/acpl- 3130, hcnw3120/3130, and sim ilar opto-drivers. the devices are ideal for driving power mosfets and igbts used in a wide va riety of inverter and motor control applications. the si826x isolated gate drivers utilize silicon laboratories' proprietary silicon isolation technology, supporting up to 5.0 kv rms withstand voltage per ul1577 and 10kv surge protection per iec60747. this technology enables higher-performance, reduced variation with temperature and age, tighter part-to-part matching, and superior co mmon-mode rejection compared to opto- coupled gate drivers. while the input ci rcuit mimics the characteristics of an led, less drive current is required, resulting in higher efficiency. propagation delay time is independent of input drive current, resu lting in consistently short propagation times, tighter unit-to-unit variation, and gr eater input circuit design flexibility. as a result, the si826x series offers longer serv ice life and dramatically higher reliability compared to opto-coupled gate drivers. ? pin-compatible, drop-in upgrades for popular high speed opto-coupled gate drivers ? low power diode emulator simplifies design-in process ? 0.6 and 4.0 amp peak output drive current ? rail-to-rail output voltage ? performance and reliability advantages vs. opto-drivers ?? resistant to temperature and age ?? 10x lower fit rate for longer service life ?? 14x tighter part-t o-part matching ?? higher common-mode transient immunity: >50 kv/s typical ? robust protection features ?? multiple uvlo ordering options (5, 8, and 12 v) with hysteresis ? 60 ns propagation delay, independent of input drive current ? wide v dd range: 6.5 to 30 v ? up to 5000 v rms isolation ? 10 kv surge withstand capability ? aec-q100 qualified ? wide operating temperature range ?? ?40 to +125 c ? rohs-compliant packages ?? soic-8 (narrow body) ?? dip8 (gull-wing) ?? sdip6 (stretched so-6) ?? lga8 ? igbt/ mosfet gate drives ? industrial, hev and renewable energy inverters ? ac, brushless, and dc motor controls and drives ? variable speed motor control in consumer white goods ? isolated switch mode and ups power supplies ? ul 1577 recognized ?? up to 5000 vrms for 1 minute ? csa component notice 5a approval ?? iec 60950-1, 61010-1, 60601-1 (reinforced insulation) ? vde certification conformity ?? iec60747-5-2/vde0884-10 (basic/reinforced insulation) ? cqc certification approval ?? gb4943.1 patent pending pin assignments: see page 22 1 2 3 4 8 7 6 5 anode cathode nc vdd vo vo soic-8, dip8, lga8 industry standard pinout gnd uvlo 1 3 6 5 4 anode cathode vdd vo gnd sdip6 industry standard pinout 2 nc uvlo e e
si826x 2 rev. 1.3 functional block diagram diode emulator i f a1 out vdd xmit gnd rec c1 output driver
si826x rev. 1.3 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. regulatory information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3.1. theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4. technical descript ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 4.1. device behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 4.2. device startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3. under voltage lockout (uvlo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5. applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1. input circuit design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2. output circuit design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3. layout considerat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.4. power dissipation considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 6. pin descriptions (soic- 8, dip8, lga8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 7. pin descriptions (sdip6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9. package outline: 8-pin narrow body so ic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 10. land pattern: 8-pin narrow body so ic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 11. package outline: dip8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 12. land pattern: dip8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 13. package outline: sdip6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 14. land pattern: sdip6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 15. package outline: lga8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 16. land pattern: lga8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 17. top markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 17.1. si826x top marking (narrow body soic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 17.2. top marking explana tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 17.3. si826x top marking (dip8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 17.4. top marking explana tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 17.5. si826x top marking (sdip6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 17.6. top marking explana tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 17.7. si826x top marking (lga8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 17.8. top marking explana tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
si826x 4 rev. 1.3 1. electrical specifications table 1. recommended operating conditions parameter symbol min typ max unit supply voltage v dd 6.5 ? 30 v input current i f(on) (see figure 1) 6?30ma operating temperature (ambient) t a ?40 ? 125 c table 2. electrical characteristics 1 v dd =15v or 30v, gnd=0v, i f =6ma, t a = ?40 to +125 c; typical specs at 25 c parameter symbol test condition min typ max unit dc parameters supply voltage 2 v dd (v dd ? gnd) 6.5 ? 30 v supply current (output high) i dd i f =10ma v dd =15v v dd =30v ? ? 1.8 2.0 2.4 2.7 ma ma supply current (output low) i dd v f =0v; i f =0ma v dd =15v v dd =30v ? ? 1.5 1.7 2.1 2.4 ma ma input current threshold i f(th) ??3.6ma input current hysteresis i hys ?0.34?ma input forward voltage (off) v f(off) measured at anode with respect to cathode. ??1v input forward voltage (on) v f(on) measured at anode with respect to cathode. 1.6 ? 2.8 v input capacitance c i f=100khz, v f =0v, v f =2v ? ? 15 15 ? ? pf output resistance high (source) 3 r oh si826xaxx devices ? 15 ? ? si826xbxx devices (i oh =-1a) ? 2.6 5.1 output resistance low (sink) 3 r ol si826xaxx devices ? 5 ? si826xbxx devices (i ol =2a) ? 0.8 2.0 notes: 1. see "8.ordering guide" on page 23 for more information. 2. minimum value of (v dd - gnd) decoupling capacitor is 1 f. 3. both v o pins are required to be shor ted together for 4.0 a compliance. 4. when performing this test, it is recommended that the dut be soldered down to the pcb to reduce parasitic inductances, which may cause over-stress conditions due to excessive ringing. 5. guaranteed by characterization.
si826x rev. 1.3 5 output high current (source) 3,4 i oh si826xaxx devices (i f =0), (t pw_ioh < 250 ns) (see figure 3) ?0.4? a si826xbxx devices (i f =0), (t pw_ioh < 250 ns), (v dd ?v o =7.5v) (see figure 3) 0.5 1.8 ? output low current (sink) 3,4 i ol si826xaxx devices (i f =10ma), (t pw_iol < 250 ns) (see figure 2) ?0.6? a si826xbxx devices (i f =10ma), (t pw_iol < 250 ns), (v o -gnd=4.2v) (see figure 2) 1.2 4.0 ? high-level output voltage v oh si826xaxx devices (i out = ?100 ma) ? v dd ? 0.4 ? v si826xbxx devices (i out = ?100 ma) v dd ? 0.5 v dd ? 0.25 ? si826xbxx devices (i out =0ma), (i f =0ma) ?v dd ? low-level output voltage v ol si826xaxx devices (i out = 100 ma), (i f =10ma) ? 320 ? mv si826xbxx devices (i out = 100 ma), (i f =10ma) ? 80 200 uvlo threshold + (si826xxax mode) vdd uv+ see figure 11 on page 16. v dd rising 55.66.3v uvlo threshold ? (si826xxax mode) vdd uv? see figure 11 on page 16. v dd falling 4.7 5.3 6.0 v uvlo lockout hysteresis (si826xxax mode) vdd hys ?300?mv table 2. electrical characteristics (continued) 1 v dd =15v or 30v, gnd=0v, i f =6ma, t a = ?40 to +125 c; typical specs at 25 c parameter symbol test condition min typ max unit notes: 1. see "8.ordering guide" on page 23 for more information. 2. minimum value of (v dd - gnd) decoupling capacitor is 1 f. 3. both v o pins are required to be shor ted together for 4.0 a compliance. 4. when performing this test, it is recommended that the dut be soldered down to the pcb to reduce parasitic inductances, which may cause over-stress conditions due to excessive ringing. 5. guaranteed by characterization.
si826x 6 rev. 1.3 uvlo threshold + (si826xxbx mode) vdd uv+ see figure 12 on page 16. v dd rising 7.5 8.4 9.4 v uvlo threshold ? (si826xxbx mode) vdd uv? see figure 12 on page 16. v dd falling 6.9 7.9 8.9 v uvlo lockout hysteresis (si826xxbx mode) vdd hys ?500?mv uvlo threshold + (si826xxcx mode) vdd uv+ see figure 13 on page 16. v dd rising 10.5 12 13.5 v uvlo threshold ? (si826xxcx mode) vdd uv? see figure 13 on page 16. v dd falling 9.4 10.7 12.2 v uvlo lockout hysteresis (si826xxcx mode) vdd hys ?1.3?v ac switching parameters input noise filter cut-off pulse width t nfc ? ? 15 ns minimum pulse width t pmin ?30?ns propagation delay (low-to-high) t plh c l = 200 pf 20 40 60 ns propagation delay (high-to-low) t phl c l = 200 pf 10 30 50 ns pulse width distortion pwd |t plh ?t phl | ? 17 28 ns propagation delay difference 5 pdd t phlmax ?t plhmin -1 ? 25 ns rise time t r c l = 200 pf ? 5.5 15 ns fall time t f c l = 200 pf ? 8.5 20 ns device startup time t start ?1630s common mode transient immunity cmti output = low or high (v cm = 1500 v), (i f > 6ma) (see figure 4) 35 50 ? kv/s table 2. electrical characteristics (continued) 1 v dd =15v or 30v, gnd=0v, i f =6ma, t a = ?40 to +125 c; typical specs at 25 c parameter symbol test condition min typ max unit notes: 1. see "8.ordering guide" on page 23 for more information. 2. minimum value of (v dd - gnd) decoupling capacitor is 1 f. 3. both v o pins are required to be shor ted together for 4.0 a compliance. 4. when performing this test, it is recommended that the dut be soldered down to the pcb to reduce parasitic inductances, which may cause over-stress conditions due to excessive ringing. 5. guaranteed by characterization.
si826x rev. 1.3 7 figure 1. diode emulator model and i-v curve figure 2. iol sink current test circuit 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 15 20 25 30 anode to cathode voltage [v] diode emulator input current [ma] 700 ? 2.2 v 10 ? anode cathode esd anode cathode e input 1 f 100 f 10 rsns 0.1 si826x 1 f cer 10 f el vdd = 15 v in out gnd vdd schottky 50 ns 200 ns measure input waveform gnd i f 9 v + _
si826x 8 rev. 1.3 figure 3. ioh source current test circuit figure 4. common mode transient immunity characterization circuit input 1 f 100 f 10 rsns 0.1 si826x 1 f cer 10 f el vdd = 15 v in out vss vdd 50 ns 200 ns measure input waveform gnd i f schottky 5.5 v + _ oscilloscope 5 v isolated supply vo 15 v supply high voltage surge generator vcm surge output high voltage differential probe gnd cathode anode input signal switch input output isolated ground 267 si826x vdd
si826x rev. 1.3 9 2. regulatory information table 3. regulatory information* csa the si826x is certified under csa component acceptanc e notice 5a. for more details, see file 232873. 61010-1: up to 600 v rms reinforced insulation working voltage; up to 600 v rms basic insulation working voltage. 60950-1: up to 1000 v rms reinforced insulation work ing voltage; up to 1000 v rms basic insulation working volt- age. 60601-1: up to 250 v rms reinforced insulation working voltage; up to 500 v rms basic insulation working voltage. vde the si826x is certified according to iec60747 and vde0884. for more details, see file 5006301-4880-0001. 60747-5-2: up to 1414 v peak for basic insulation working voltage. vde0884-10: up to 1414 v peak for reinforced insula tion working voltage. ul the si826x is certified under ul15 77 component recognition program. for more details, see file e257455. rated up to 5000 v rms isolation voltage for basic protection. cqc the si826x is certified under gb 4943.1-2011. for more details, see certificates cqc14001104575, cqc15001121282 and cqc15001121283. rated up to 1000 v rms reinforced insulation working voltage; up to 1000 v rms basic insulation working voltage. *note: regulatory certifications apply to 3.75 kv rms rated devices which are production tested to 4.5 kv rms for 1 sec. regulatory certificat ions apply to 5.0 kv rms rated devices which are production tested to 6.0 kv rms for 1 sec. for more information, see "8.ordering guide" on page 23. table 4. insulation and safety-related specifications parameter symbol test condition value unit soic-8 dip8 sdip6 lga8 nominal air gap (clearance) l(io1) 4.7 min 7.2 min 9.6 min 10.0 min mm nominal external tracking (creepage) l(io2) 3.9 min 7.0 min 8.3 min 10.0 min mm minimum internal gap (internal clearance) 0.016 0.016 0.016 0.016 mm tracking resistance (proof tracking index) pti iec60112 600 600 600 600 v erosion depth ed 0.031 0.031 0.057 0.021 mm resistance (input-output)* r io 10 12 10 12 10 12 10 12 ? capacitance (input-output)* c io f=1mhz1111pf *note: to determine resistance and capacitance, the si826x is conv erted into a 2-terminal device. pins 1?4 (1?3, sdip6) are shorted together to form the first terminal, and pins 5?8 (4?6 , sdip6) are shorted together to form the second terminal. the parameters are then measured between these two terminals.
si826x 10 rev. 1.3 table 5. iec 60664-1 (vde 0884) ratings parameter test conditions specification soic-8 dip8 sdip6 lga8 basic isolation group material group i i i i installation classification rated mains voltages < 150 v rms i-iv i-iv i-iv i-iv rated mains voltages < 300 v rms i-iv i-iv i-iv i-iv rated mains voltages < 450 v rms i-iii i-iii i-iv i-iv rated mains voltages < 600 v rms i-iii i-iii i-iv i-iv rated mains voltages < 1000 v rms i-ii i-ii i-iii i-iii table 6. iec 60747-5-2 (vde 0884-10) insulation characteristics* parameter symbol test condition characteristic unit soic-8 dip8 sdip6 lga8 maximum working insulation voltage v iorm 630 891 1140 1414 v peak input to output test voltage v pr method b1 (v iorm x 1.875 = v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc) 1181 1671 2138 2652 v peak transient overvoltage v iotm t = 60 sec 6000 6000 8000 8000 v peak pollution degree (din vde 0110, table 1) 2222 insulation resistance at t s , v io =500v r s >10 9 >10 9 >10 9 >10 9 ? *note: this isolator is suitable for reinforced electrical isolati on only within the safety limit data. maintenance of the safety data is ensured by protective circuits. the si826x provides a climate classification of 40/125/21. table 7. iec safety limiting values* parameter symbol test condition max unit soic-8 dip8 sdip6 lga8 case temperature t s 140 140 140 140 c input current i s ? ja = 110 c/w (soic-8), 110 c/w (dip8), 105 c/w (sdip6), 220 c (lga8), v f =2.8v, t j =140c, t a =25c 370 370 390 185 ma output power p s 1110.5w *note: maximum value allowed in the event of a failure; also see the thermal derating curve in figures 5, 6, 7, and 8.
si826x rev. 1.3 11 figure 5. (soic-8) thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 and vde0884-10 figure 6. (dip8) thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 and vde0884-10 table 8. thermal characteristics parameter symbol typ unit soic-8 dip8 sdip6 lga8 ic junction-to-air thermal resistance ? ja 110 110 105 220 oc/w 400 600 800 1000 1200 ower r ps, input current r is ps (mw) is (ma) 0 200 0 20406080100120140 output po ts r case temperature (c) 400 600 800 1000 1200 ower r ps, input current r is ps (mw) is (ma) 0 200 0 20406080100120140 output po ts r case temperature (c)
si826x 12 rev. 1.3 figure 7. (sdip6) thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 and vde0884-10 figure 8. (lga8) thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 and vde0884-10 400 600 800 1000 1200 ower r ps, input current r is ps (mw) is (m a) 0 200 0 20406080100120140 output po ts r case temperature (c) 200 300 400 500 600 o wer r ps, input current r is ps (mw) is (ma) 0 100 0 20406080100120140 output p o ts r case temperature (c)
si826x rev. 1.3 13 table 9. absolute maximum ratings* parameter symbol min max unit storage temperature t stg ?65 +150 c operating temperature t a ?40 +125 c junction temperature t j ?+140c average forward input current i f(avg) ?30ma peak transient input current (< 1 s pulse width, 300 ps) i ftr ?1 a reverse input voltage v r ?0.3 v supply voltage vdd ?0.5 36 v output voltage v out ?0.5 36 v peak output current (t pw = 10 s, duty cycle = 0.2%) (0.6 amp versions) i opk ?0.6 a peak output current (t pw = 10 s, duty cycle = 0.2%) (4.0 amp versions) i opk ?4.0 a input power dissipation p i ?75mw output power dissipation p o ?225mw total power dissipation (all packages limited by thermal derating curve) p t ?300mw lead solder temperature (10 s) ? 260 c hbm rating esd 4 ? kv machine model esd 300 ? v cdm 2000 ? v maximum isolation voltage (1 s) soic-8 ? 4500 v rms maximum isolation voltage (1 s) dip8 ? 6500 v rms maximum isolation voltage (1 s) sdip6 ? 6500 v rms maximum isolation voltage (1 s) lga8 ? 6500 v rms *note: permanent device damage may occur if the absolute maximu m ratings are exceeded. functional operation should be restricted to the conditions specified in the operational sections of this data sheet.
si826x 14 rev. 1.3 3. functional description 3.1. theory of operation the si826x is a functional upgrade for popular opto-isola ted drivers, such as the avago hpcl-3120, hpcl-0302, toshiba tlp350, and others. the operation of an si826x chann el is analogous to that of an opto coupler, except an rf carrier is modulated inste ad of light. this simple architecture provid es a robust isolated data path and requires no special considerations or initializ ation at start-up. the si826x also in cludes a noise filter that suppresses propagation of any pulse narrower than 15 ns. a simplifi ed block diagram for the si826x is shown in figure 9. figure 9. simplified channel diagram rf oscillator modulator demodulator + noise filter a b semiconductor- based isolation barrier transmitter receiver led emulator 0.6 to 4.0 a peak gnd v dd
si826x rev. 1.3 15 4. technical description 4.1. device behavior truth tables for the si826x are summarized in table 10. 4.2. device startup output v o is held low during power-up until v dd rises above the uvlo+ threshold for a minimum time period of t start . following this, the output is high when the current flowing from anode to cathode is > i f(on) . device startup, normal operation, and shutdown behavior is shown in figure 10. figure 10. si826x operating behavior (i f > i f(min) when v f > v f(min) ) table 10. si826x truth table summary* input v dd v o off > uvlo low off < uvlo low on > uvlo high on < uvlo low *note: this truth table assumes vdd is powered. if vdd is below uvlo, see "4.3.under voltage lockout (uvlo)" on page 16 for more information. i f v o v dd t start t start v ddhys t phl t plh i f(on) uvlo+ uvlo- i hys
si826x 16 rev. 1.3 4.3. under voltage lockout (uvlo) the uvlo circuit unconditionally drives v o low when v dd is below the lockout thresh old. referring to figures 11 through 13, upon power up, the si826x is main tained in uvlo unt il vdd rises above vdd uv+ . during power down, the si826x enters uvlo when vdd falls below th e uvlo threshold plus hy steresis (i.e., vdd < vdd uv+ ? vdd hys ). figure 11. si826xxax uvlo response (5 v) figure 12. si826xxbx uvlo response (8 v) figure 13. si826xxcx uvlo response (12 v) 3.5 v dduv+ (typ) output voltage (v o ) 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 supply voltage (v dd - gnd) (v) 6.0 v dduv+ (typ) output voltage (v o ) 6.57.0 7.58.0 8.5 9.09.510.0 supply voltage (v dd - gnd) (v) 9.5 v dduv+ (typ) output voltage (v o ) 10.0 10.5 11.0 11.5 12.0 12.5 13.0 supply voltage (v dd - gnd) (v)
si826x rev. 1.3 17 5. applications the following sections detail the input and output circuits necessary for proper oper ation. power dissipation and layout considerations are also discussed. 5.1. input circuit design opto driver manufacturers typically recommend the circ uits shown in figures 14 and 15. these circuits are specifically designed to improve op to-coupler input common-mode rejection and increase noise immunity. figure 14. si826x input circuit figure 15. high cmr si826x input circuit the optically-coupled driver circuit of figure 14 turns the led on when the control input is high. however, internal capacitive coupling from the led to the power and ground conductors can momentarily force the led into its off state when the anode and cathode inputs are subjected to a high common-mode transient. the circuit shown in figure 15 addresses this issue by using a value of r1 suff iciently low to overdrive the led, ensuring it remains on during an input common-mode transient. q1 shorts the led off in the low output state, again increasing common- mode transient immunity. some opto driver applications recommend reverse-biasing th e led when the control input is off to prevent coupled noise from energizing the led. the si826x input circui t requires less current and has twice the off-state noise margin compared to opto couplers. however, high cmr opto coupler designs that overdrive the led (see figure 15) may require increasing the value of r1 to limit input current i f to its maximum rating when using the si826x. in addition, there is no benefit in driving the si82 6x input diode into reverse bias when in the off state. r1 1 2 3 4 si826x vext open drain or collector control input anode cathode n/c n/c r1 1 2 3 4 si826x vext control input anode cathode n/c n/c q1
si826x 18 rev. 1.3 consequently, opto coupler circuits usi ng this technique should either leave the negative bias circuitry unpopulated or modify the circuitry (e.g., add a clamp diode or curren t limiting resistor) to ensure that the anode pin of the si826x is no more than ?0.3 v with resp ect to the cathode when reverse-biased. new designs should consider the input circuit configuratio ns of figure 16, which are mo re efficient than those of figures 14 and 15. as shown, s1 and s2 represent any suitable switch, such as a bjt or mosfet, analog transmission gate, processor i/o, etc. al so, note that the si826x input can be driven from the i/o port of any mcu or fpga capable of sourcing a minimum of 6 ma (see figu re 16c). additionally, note that the si826x propagation delay and output drive do not significantly change for values of i f between i f(min) and i f(max) . figure 16. si826x other input circuit configurations 5.2. output circuit design gnd can be biased at, above, or below ground as long as the voltage on v dd with respect to gnd is a maximum of 30 v. v dd decoupling capacitors should be placed as close to the package pins as possible. the optimum values for these capacitors depend on load current and t he distance between the chip and its power source. it is recommended that 0.1 and 10 f bypass capacitors be used to reduce high-frequency noise and maximize performance. 5.3. layout considerations it is most important to minimize ringing in the drive path and noise on the v dd lines. care must be taken to minimize parasitic inductance in these pa ths by locating the si826x as close as possible to the device it is driving. in addition, the v dd supply and ground trace paths must be kept short. for this reason, the use of power and ground planes is highly recommended. a split gr ound plane system having separate ground and v dd planes for power devices and small signal components provides the best overall noise performance. control input vext r1 s1 n/c anode cathode n/c see text si826x a 4 3 2 1 si826x 1 2 3 4 vext control input s1 n/c anode cathode n/c b r1 s2 si826x c 4 n/c 3 cathode 2 mcu i/o port pin anode r1 1 n/c
si826x rev. 1.3 19 5.4. power dissipation considerations proper system design must assure that the si826x operates within safe therma l limits across the entire load range. the si826x total power dissipation is the sum of the powe r dissipated by bias supply current, internal switching losses, and power delivered to the load, as shown in equation 1. equation 1. the maximum allowable power dissipation for the si826x is a function of the package thermal resistance, ambient temperature, and maximum allowable juncti on temperature, as shown in equation 2. equation 2. substituting values for p dmax t jmax , t a , and ? ja into equation 2 results in a maximum allowable total power dissipation of 1.0 w. note that the ma ximum allowable load is found by substituting this limit and the appropriate datasheet values from table 2 on page 4 into equation 1 and simplifying. graphs are shown in figures 17 and 18. all points along the load lines in these graphs re present the package dissipation-limited value of c l for the corresponding switching frequency. p d i f v f ? dc ? v dd + i ddq q d c l + v dd ? ?? + f ? ?? ? where: p d is the total device power dissipation (w) i f is the diode current (30 ma max) v f is the diode anode to cathode voltage (2.8 v max) dc is duty cycle (0.5 typical) v dd is the driver-side su pply voltage (30 v max) i ddq is the driver maximum bias current (2.5 ma) q d is 3 nc c l is the load capacitance f is the switching frequency (hz) = p dmax t jmax t a ? ? ja --------------------------- where: p dmax is the maximum allowable power dissipation (w) t jmax is the maximum junction temperature (140 c) t a is the ambient temperature (c) ? ja is the package junction-to-air thermal resistance (110 c/w) ?
si826x 20 rev. 1.3 figure 17. (soic-8, dip8, sdip6) maximum load vs. switching frequency (25 c) figure 18. (lga8) maximum load vs. switching frequency (25 c) 0.1 1.0 10.0 100.0 1000.0 10000.0 10 100 1000 max load (nf) frequency (khz) 7v 12v 18v 30v 0.1 1.0 10.0 100.0 1000.0 10000.0 10 100 1000 max load (nf) frequency (khz) 7v 12v 18v 30v
si826x rev. 1.3 21 6. pin descriptions (soic-8, dip8, lga8) figure 19. pin configuration table 11. pin descriptions (soic-8, dip8, lga8) pin name description 1 nc* no connect. 2 anode anode of led emulator. v o follows the signal applied to this input with respect to the cathode input. 3 cathode cathode of led emulator. v o follows the signal applied to an ode with respect to this input. 4 nc* no connect. 5 gnd external mosfet source connection and ground reference for v dd . this terminal is typically connected to ground but may be tied to a negative or positive voltage. 6v o output signal. both v o pins are required to be shorted together for 4.0 a compliance. 7v o output signal. both v o pins are required to be shorted together for 4.0 a compliance. 8v dd output-side power supply input referenced to gnd (30 v max). *note: no connect. these pins are not internally connected. to maximize cmti performance, these pins should be connected to the ground plane. 1 2 3 4 8 7 6 5 nc anode cathode nc vdd vo vo soic-8, dip8, lga8 industry standard pinout gnd uvlo e
si826x 22 rev. 1.3 7. pin descriptions (sdip6) figure 20. pin configuration table 12. pin descriptions (sdip6) pin name description 1 anode anode of led emulator. v o follows the signal applied to this input with respect to the cathode input. 2 nc* no connect. 3 cathode cathode of led emulator. v o follows the signal applied to an ode with respect to this input. 4 gnd external mosfet source connection and ground reference for v dd . this terminal is typically connected to ground but may be tied to a negative or positive voltage. 5v o output signal. 6v dd output-side power supply input referenced to gnd (30 v max). *note: no connect. these pins are not internally connected. to maximize cmti performance, these pins should be connected to the ground plane. 1 3 6 5 4 anode cathode vdd vo gnd sdip6 industry standard pinout 2 nc uvlo e
si826x rev. 1.3 23 8. ordering guide table 13. si826x ordering guide 1,2,3 new ordering part number (opn) ordering options output configuration cross reference uvlo voltage insulation rating temp range pkg type SI8261AAC-C-IS 0.6 a driver hcpl-0314 5 v 3.75 kvrms ?40 to +125 c soic-8 si8261bac-c-is 4.0 a driver ? 5 v 3.75 kvrms ?40 to +125 c soic-8 si8261aac-c-ip 0.6 a driver hcpl-3140 5 v 3.75 kvrms ?40 to +125 c dip8/gw si8261bac-c-ip 4.0 a driver tlp 350 hcpl-3120 5 v 3.75 kvrms ?40 to +125 c dip8/gw si8261aad-c-is 0.6 a driv er acpl-w314 5 v 5.0 kvrms ?40 to +125 c sdip6 si8261bad-c-is 4.0 a driver tlp 700f 5 v 5.0 kvrms ?40 to +125 c sdip6 si8261aad-c-im 0.6 a driver ? 5 v 5.0 kvrms ?40 to +125 c lga8 si8261bad-c-im 4.0 a driver hcnw-3120 5 v 5.0 kvrms ?40 to +125 c lga8 notes: 1. all packages are rohs-compliant with peak solder reflow te mperatures of 260 c according to the jedec industry standard classifications. 2. ?si? and ?si? are used interchangeably. 3. aec-q100 qualified.
si826x 24 rev. 1.3 si8261abc-c-is 0.6 a driver hcpl-0314 8 v 3.75 kvrms ?40 to +125 c soic-8 si8261bbc-c-is 4.0 a driver ? 8 v 3.75 kvrms ?40 to +125 c soic-8 si8261abc-c-ip 0.6 a driver hcpl-3140 8 v 3.75 kvrms ?40 to +125 c dip8/gw si8261bbc-c-ip 4.0 a driver tlp 350 hcpl-3120 8 v 3.75 kvrms ?40 to +125 c dip8/gw si8261abd-c-is 0.6 a driv er acpl-w314 8 v 5.0 kvrms ?40 to +125 c sdip6 si8261bbd-c-is 4.0 a driver tlp 700f 8 v 5.0 kvrms ?40 to +125 c sdip6 si8261abd-c-im 0.6 a driver ? 8 v 5.0 kvrms ?40 to +125 c lga8 si8261bbd-c-im 4.0 a driver hcnw-3120 8 v 5.0 kvrms ?40 to +125 c lga8 table 13. si826x ordering guide 1,2,3 new ordering part number (opn) ordering options output configuration cross reference uvlo voltage insulation rating temp range pkg type notes: 1. all packages are rohs-compliant with peak solder reflow te mperatures of 260 c according to the jedec industry standard classifications. 2. ?si? and ?si? are used interchangeably. 3. aec-q100 qualified.
si826x rev. 1.3 25 si8261acc-c-is 0.6 a driver hcpl-0314 12 v 3.75 kvrms ?40 to +125 c soic-8 si8261bcc-c-is 4.0 a driver ? 12 v 3.75 kvrms ?40 to +125 c soic-8 si8261acc-c-ip 0.6 a driver hcpl-3140 12 v 3.75 kvrms ?40 to +125 c dip8/gw si8261bcc-c-ip 4.0 a driver tlp 350 hcpl-3120 12 v 3.75 kvrms ?40 to +125 c dip8/gw si8261acd-c-is 0.6 a driver acpl-w314 12 v 5.0 kvrms ?40 to +125 c sdip6 si8261bcd-c-is 4.0 a driver tlp 700f 12 v 5.0 kvrms ?40 to +125 c sdip6 si8261acd-c-im 0.6 a driver ? 12 v 5.0 kvrms ?40 to +125 c lga8 si8261bcd-c-im 4.0 a driver hcnw-3120 12 v 5.0 kvrms ?40 to +125 c lga8 table 13. si826x ordering guide 1,2,3 new ordering part number (opn) ordering options output configuration cross reference uvlo voltage insulation rating temp range pkg type notes: 1. all packages are rohs-compliant with peak solder reflow te mperatures of 260 c according to the jedec industry standard classifications. 2. ?si? and ?si? are used interchangeably. 3. aec-q100 qualified.
si826x 26 rev. 1.3 9. package outline: 8-pin narrow body soic figure 21 illustrates the package details for the si826x in an 8- pin narrow-body soic pack age. table 14 lists the values for the di mensions shown in the illustration. figure 21. 8-pin narrow body soic package table 14. 8-pin narrow body soic package diagram dimensions symbol millimeters min max a1.351.75 a1 0.10 0.25 a2 1.40 ref 1.55 ref b0.330.51 c0.190.25 d4.805.00 e3.804.00 e 1.27 bsc h5.806.20 h0.250.50 l0.401.27 ? 0 ? 8 ? ?
si826x rev. 1.3 27 10. land pattern: 8-pin narrow body soic figure 22 illustrates the recommended land pattern details for the si826x in an 8-pin narrow-body soic. table 15 lists the values for the dimens ions shown in the illustration. figure 22. 8-pin narrow body soic land pattern table 15. 8-pin narrow body soic land pattern dimensions dimension feature (mm) c1 pad column spacing 5.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.55 notes: 1. this land pattern design is based on ipc-7351 pattern soic127p600x173-8n for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed.
si826x 28 rev. 1.3 11. package outline: dip8 figure 23 illustrates the package details for the si826x in a dip8 package . table 16 lists the values for the dimensions shown in the illustration. figure 23. dip8 package table 16. dip8 package diagram dimensions dimension min max a ? 4.19 a1 0.55 0.75 a2 3.17 3.43 b 0.35 0.55 b2 1.14 1.78 b3 0.76 1.14 c 0.20 0.33 d 9.40 9.90 e 7.37 7.87 e1 6.10 6.60 e2 9.40 9.90 e 2.54 bsc. l 0.38 0.89 aaa ? 0.25 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994.
si826x rev. 1.3 29 12. land pattern: dip8 figure 24 illustrates the recommended land pattern de tails for the si826x in a dip8 package. table 17 lists the values for the di mensions shown in the illustration. figure 24. dip8 land pattern table 17. dip8 land pattern dimensions* dimension min max c8.858.90 e2.54 bsc x0.600.65 y1.651.70 *note: this land pattern design is based on the ipc-7351 specification. ?
si826x 30 rev. 1.3 13. package outline: sdip6 figure 25 illustrates the package details for the si826x in an sdip6 package . table 18 lists the values for the dimensions shown in the illustration. figure 25. sdip6 package table 18. sdip6 package diagram dimensions dimension min max a?2.65 a1 0.10 0.30 a2 2.05 ? b0.310.51 c0.200.33 d 4.58 bsc e 11.50 bsc e1 7.50 bsc e 1.27 bsc notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994.
si826x rev. 1.3 31 l0.401.27 h0.250.75 0 8 aaa ? 0.10 bbb ? 0.33 ccc ? 0.10 ddd ? 0.25 eee ? 0.10 fff ? 0.20 table 18. sdip6 package diagram dimensions (continued) dimension min max notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994.
si826x 32 rev. 1.3 14. land pattern: sdip6 figure 26 illustrates the recommended land pattern details for the si826x in an sdip6 package. table 19 lists the values for the di mensions shown in the illustration. figure 26. sdip6 land pattern table 19. sdip6 land pattern dimensions* dimension min max c 10.45 10.50 e1.27 bsc x0.550.60 y2.002.05 *note: this land pattern design is based on the ipc-7351 specification. ?
si826x rev. 1.3 33 15. package outline: lga8 figure 27 illustrates the packag e details for the si8 26x in an lga8 package. tabl e 20 lists the values for the dimensions shown in the illustration. figure 27. lga8 package table 20. package diagram dimensions dimension min nom max a 0.74 0.84 0.94 b 1.15 1.20 1.25 d 10.00 bsc. e 2.54 bsc. e 12.50 bsc. l 1.05 1.10 1.15 l1 0.05 0.10 0.15 aaa ? ? 0.10 bbb ? ? 0.10 ccc ? ? 0.10 ddd ? ? 0.10 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. ?
si826x 34 rev. 1.3 16. land pattern: lga8 figure 28 illustrates the recomm ended land pattern details fo r the si826x in an lga8 package. table 21 lists the values for the di mensions shown in the illustration. figure 28. lga8 land pattern table 21. lga8 land pattern dimensions dimension feature (mm) c1 pad column spacing 11.80 e pad row pitch 2.54 x1 pad width 1.30 y1 pad length 1.80 notes: 1. this land pattern design is based on ipc-7351 specifications. 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed. ?
si826x rev. 1.3 35 17. top markings 17.1. si826x top marking (narrow body soic) 17.2. top marking explanation line 1 marking: customer part number 826 = isodriver product series c = input configuration 1 = opto input type i = peak output current a=0.6a; b=4.0a u = uvlo level a = 5 v; b = 8 v; c = 12 v v = isolation rating c = 3.75 kv; d = 5.0 kv line 2 marking: rttttt = mfg code manufacturing code from the assembly purchase order form. ?r? indicates revision. line 3 marking: circle = 43 mils diameter left-justified ?e4? pb-free symbol yy = year ww = work week assigned by the assembly house. corresponds to the year and work week of the mold date.
si826x 36 rev. 1.3 17.3. si826x top marking (dip8) 17.4. top marking explanation line 1 marking: customer part number si826 = isodriver product series c = input configuration 1 = opto input type i = peak output current a=0.6a; b=4.0a u = uvlo level a = 5 v; b = 8 v; c = 12 v v = isolation rating c = 3.75 kv; d = 5.0 kv line 2 marking: yy = year ww = work week assigned by the assembly house. corresponds to the year and work week of the mold date. rttttt = mfg code manufacturing code from the assembly purchase order form. ?r? indicates revision. line 3 marking: circle = 51 mils diameter center-justified ?e4? pb-free symbol co = country of origin country of origin iso code abbreviation
si826x rev. 1.3 37 17.5. si826x top marking (sdip6) 17.6. top marking explanation line 1 marking: device si826 = isodriver product series c = input configuration 1 = opto input type line 2 marking: device rating i = peak output current a=0.6a; b=4.0a u = uvlo level a = 5 v; b = 8 v; c = 12 v v = isolation rating c = 3.75 kv; d = 5.0 kv line 3 marking: rttttt = mfg code manufacturing code from the assembly purchase order form. ?r? indicates revision. line 4 marking: yy = year ww = work week assigned by the assembly house. corresponds to the year and work week of the mold date.
si826x 38 rev. 1.3 17.7. si826x top marking (lga8) 17.8. top marking explanation line 1 marking: device part number si826 = isodriver product series c = input configuration 1 = opto input type i = peak output current a=0.6a; b=4.0a u = uvlo level a = 5 v; b = 8 v; c = 12 v v = isolation rating c = 3.75 kv; d = 5.0 kv line 2 marking: yy = year ww = work week assigned by the assembly house. corre- sponds to the year and work week of the assembly release. rttttt = mfg code manufacturing code from the assembly pur- chase order form. ?r? indicates revision. line 3 marking: circle = 1.6 mm diameter center-justified ?e4? pb-free symbol co = country of origin country of origin iso code abbreviation line 4 marking: circle = 0.75 mm diameter lower left-justified pin 1 identifier
si826x rev. 1.3 39 d ocument c hange l ist revision 0.9 to revision 1.0 ? updated table 2 on page 4. ? added figure 1 on page 7. ? updated "3.1.theory of operation" on page 14. ? updated figures 11, 12, and 13 on page 16. ? removed ?5.5. parametric differences between si826x and hcpl-0302 and hcpl-3120 opto drivers?. revision 1.0 to revision 1.1 ? updated figure 1 on page 7. ? updated ordering guide table 13 on page 23. ?? removed references to moisture sensitivity levels from table note. revision 1.1 to revision 1.2 ? removed ?sampling? from ordering guide table 13 on page 23. revision 1.2 to revision 1.3 ? updated table 3 on page 9. ?? added cqc certificate numbers. ? updated table 5 on page 10. ?? updated rated mains voltage for 1000 v rms ratings. ? updated table 6 on page 10. ?? removed v iosm specification. ? updated table 9 on page 13. ?? replaced i o with peak output current i opk . ? updated figure 14 on page 17. ? updated figure 15 on page 17. ? updated figure 16 on page 18. ? changed v dd minimum throughout document to reflect 6.5 v, not 5 v, as normal operation.
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